Energy-Aware SYstem-on-chip design of the HIPERLAN/2 standard

This deliverable presents several methodologies and preliminary experimental results regarding the design of low-power memory subsystems. The existing literature is first reviewed in order to identify the class of memory design approaches that are most suitable to the EASY project, namely, those which are applicable in the context of the HIPERLAN/2 SoC development and, at the same time, are general enough to guarantee the implementation of a general-purpose memory design prototype tool. A memory partitioning algorithm is then described in details, together with enhancement techniques that make its use more effective. Preliminary experimental results, collected on some benchmarks, show the usability of the proposed strategy. Copyright  2002 ICOM POLITO UP FhG IIS-A STM IMEC AUTH IST-2000-30093 Low-power memory partitioning and buffering techniques EASY/WP3/POLITO/DL/P/D16/B1 Public 2 History Date Version Comments August 21, 2002 1 First draft, survey section only August 28, 2002 2 Added methodology section August 30, 2002 3 Added partitioning results September 10, 2002 4 Added address clustering section September 13, 2002 5 Version submitted to consortium September 18, 2002 6 Project Approved IST-2000-30093 Low-power memory partitioning and buffering techniques EASY/WP3/POLITO/DL/P/D16/B1 Public 3 Table of contents LIST OF TABLES AND FIGURES..................................................................................................................4